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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/ldr.isa | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 9211983d4..a346c495a 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -106,7 +106,11 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; - URc = cpsr | CondCodesF | CondCodesGE; + cpsr.nz = CondCodesNZ; + cpsr.c = CondCodesC; + cpsr.v = CondCodesV; + cpsr.ge = CondCodesGE; + URc = cpsr; URa = cSwap<uint32_t>(Mem.ud, cpsr.e); URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e); ''' @@ -137,7 +141,7 @@ let {{ def __init__(self, *args, **kargs): super(LoadRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType); |