ARM: Define the load instructions from outside the decoder.

1 files changed, 143 insertions, 0 deletions

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
new file mode 100644
index 000000000..17f8bdef4
--- /dev/null
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -0,0 +1,143 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+let {{
+
+    header_output = ""
+    decoder_output = ""
+    exec_output = ""
+
+    def loadImmClassName(post, add, writeback, \
+                         size=4, sign=False, user=False):
+        return memClassName("LOAD_IMM", post, add, writeback,
+                            size, sign, user)
+
+    def loadRegClassName(post, add, writeback, \
+                         size=4, sign=False, user=False):
+        return memClassName("LOAD_REG", post, add, writeback,
+                            size, sign, user)
+
+    def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
+        global header_output, decoder_output, exec_output
+
+        (newHeader,
+         newDecoder,
+         newExec) = newLoadStoreBase(name, Name, imm,
+                                     eaCode, accCode,
+                                     memFlags, instFlags,
+                                     base, execTemplateBase = 'Load')
+
+        header_output += newHeader
+        decoder_output += newDecoder
+        exec_output += newExec
+
+    def buildImmLoad(mnem, post, add, writeback, \
+                     size=4, sign=False, user=False):
+        name = mnem
+        Name = loadImmClassName(post, add, writeback, \
+                                size, sign, user)
+
+        if add:
+            op = " +"
+        else:
+            op = " -"
+
+        offset = op + " imm"
+        eaCode = "EA = Base"
+        if not post:
+            eaCode += offset
+        eaCode += ";"
+
+        accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
+        if writeback:
+            accCode += "Base = Base %s;\n" % offset
+        base = buildMemBase("MemoryNewImm", post, writeback)
+
+        emitLoad(name, Name, True, eaCode, accCode, [], [], base)
+
+    def buildRegLoad(mnem, post, add, writeback, \
+                     size=4, sign=False, user=False):
+        name = mnem
+        Name = loadRegClassName(post, add, writeback,
+                                size, sign, user)
+
+        if add:
+            op = " +"
+        else:
+            op = " -"
+
+        offset = op + " shift_rm_imm(Index, shiftAmt," + \
+                      " shiftType, CondCodes<29:>)"
+        eaCode = "EA = Base"
+        if not post:
+            eaCode += offset
+        eaCode += ";"
+
+        accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
+        if writeback:
+            accCode += "Base = Base %s;\n" % offset
+        base = buildMemBase("MemoryNewReg", post, writeback)
+
+        emitLoad(name, Name, False, eaCode, accCode, [], [], base)
+
+    def buildLoads(mnem, size=4, sign=False, user=False):
+        buildImmLoad(mnem, True, True, True, size, sign, user)
+        buildRegLoad(mnem, True, True, True, size, sign, user)
+        buildImmLoad(mnem, True, False, True, size, sign, user)
+        buildRegLoad(mnem, True, False, True, size, sign, user)
+        buildImmLoad(mnem, False, True, True, size, sign, user)
+        buildRegLoad(mnem, False, True, True, size, sign, user)
+        buildImmLoad(mnem, False, False, True, size, sign, user)
+        buildRegLoad(mnem, False, False, True, size, sign, user)
+        buildImmLoad(mnem, False, True, False, size, sign, user)
+        buildRegLoad(mnem, False, True, False, size, sign, user)
+        buildImmLoad(mnem, False, False, False, size, sign, user)
+        buildRegLoad(mnem, False, False, False, size, sign, user)
+
+    buildLoads("ldr")
+    buildLoads("ldrt", user=True)
+    buildLoads("ldrb", size=1)
+    buildLoads("ldrbt", size=1, user=True)
+    buildLoads("ldrsb", size=1, sign=True)
+    buildLoads("ldrsbt", size=1, sign=True, user=True)
+    buildLoads("ldrh", size=2)
+    buildLoads("ldrht", size=2, user=True)
+    buildLoads("hdrsh", size=2, sign=True)
+    buildLoads("ldrsht", size=2, sign=True, user=True)
+}};