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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3 (patch) | |
| tree | 273490f7ecbdbf3dc6f89d3ef46c46c7f07bc24c /src/arch/arm/isa/insts/ldr.isa | |
| parent | 3aea20d143ee27e0562f6f9ea3d4c1b4bbfd20f3 (diff) | |
| download | gem5-b8ec21455382c3b5e0e9bc8c0dbcd38b07c567e3.tar.xz | |
ARM: Implement ARM CPU interrupts
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index f5ea53b72..40d9147df 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -137,11 +137,12 @@ let {{ wbDiff = 8 accCode = ''' CPSR cpsr = Cpsr; + SCTLR sctlr = Sctlr; NPC = cSwap<uint32_t>(Mem.ud, cpsr.e); uint32_t newCpsr = cpsrWriteByInstr(cpsr | CondCodes, cSwap<uint32_t>(Mem.ud >> 32, cpsr.e), - 0xF, true); + 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodes = CondCodesMask & newCpsr; ''' |