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authorAli Saidi <Ali.Saidi@ARM.com>2010-08-25 19:10:43 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-08-25 19:10:43 -0500
commitedca5f7da6bad677dfc1ea69fff904554181cc17 (patch)
tree19e1656c6267c6677944160d10ea1a229f409b94 /src/arch/arm/isa/insts/ldr.isa
parente6d3fe8a0c02e0692444399e63e6c5ce6c3abd17 (diff)
downloadgem5-edca5f7da6bad677dfc1ea69fff904554181cc17.tar.xz
ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 38a458b23..dc043ed8e 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -67,7 +67,7 @@ let {{
self.memFlags = ["ArmISA::TLB::MustBeOne"]
self.codeBlobs = {"postacc_code" : ""}
- def emitHelper(self, base = 'Memory', wbDecl = None):
+ def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = []):
global header_output, decoder_output, exec_output
@@ -76,7 +76,7 @@ let {{
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags, [], base, wbDecl)
+ self.memFlags, instFlags, base, wbDecl)
header_output += newHeader
decoder_output += newDecoder
@@ -118,7 +118,7 @@ let {{
wbDecl = None
if self.writeback:
wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
- self.emitHelper('RfeOp', wbDecl)
+ self.emitHelper('RfeOp', wbDecl, ["IsSerializeAfter", "IsNonSpeculative"])
class LoadImmInst(LoadInst):
def __init__(self, *args, **kargs):