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authorAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:27 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-04-04 11:42:27 -0500
commitbe096f91b94ded36f43dd7d547a5671f99a264b1 (patch)
tree85442361558d1123c441538a173dabc9a3fa0a6c /src/arch/arm/isa/insts/ldr.isa
parent55920a5ca73ded58762f1b7ae25c8cfe8c9e407d (diff)
downloadgem5-be096f91b94ded36f43dd7d547a5671f99a264b1.tar.xz
ARM: Tag appropriate instructions as IsReturn
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 2e45f2875..bfa94103f 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -58,6 +58,7 @@ let {{
self.sign = sign
self.user = user
self.flavor = flavor
+ self.rasPop = False
if self.add:
self.op = " +"
@@ -77,7 +78,7 @@ let {{
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
self.memFlags, instFlags, base,
- wbDecl, pcDecl)
+ wbDecl, pcDecl, self.rasPop)
header_output += newHeader
decoder_output += newDecoder
@@ -128,6 +129,10 @@ let {{
else:
self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
+ if self.add and self.post and self.writeback and not self.sign and \
+ not self.user and self.size == 4:
+ self.rasPop = True
+
class LoadRegInst(LoadInst):
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)