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authorGabe Black <gblack@eecs.umich.edu>2010-12-09 14:45:17 -0800
committerGabe Black <gblack@eecs.umich.edu>2010-12-09 14:45:17 -0800
commit2ff3e6b399796a182b3c9cb68f021d1f533356e4 (patch)
tree157f0930a9047292cf0d0a2e64de8425b23559ed /src/arch/arm/isa/insts/ldr.isa
parent24c5b5925d0bc724a9c6f3f4582def33e113ccf0 (diff)
downloadgem5-2ff3e6b399796a182b3c9cb68f021d1f533356e4.tar.xz
ARM: Take advantage of new PCState syntax.
Diffstat (limited to 'src/arch/arm/isa/insts/ldr.isa')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index b091da856..21601f7d3 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -105,16 +105,15 @@ let {{
accCode = '''
CPSR cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- ArmISA::PCState pc = PCS;
- pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e));
+ // Use the version of NPC that gets set before NextThumb
+ pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
uint32_t newCpsr =
cpsrWriteByInstr(cpsr | CondCodes,
cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
0xF, true, sctlr.nmfi);
Cpsr = ~CondCodesMask & newCpsr;
- pc.nextThumb(((CPSR)newCpsr).t);
- pc.nextJazelle(((CPSR)newCpsr).j);
- PCS = pc;
+ NextThumb = ((CPSR)newCpsr).t;
+ NextJazelle = ((CPSR)newCpsr).j;
CondCodes = CondCodesMask & newCpsr;
'''
self.codeBlobs["memacc_code"] = accCode