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| author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
|---|---|---|
| committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
| commit | af6aaf258171027af8d3cf0ef86dddff501a3ccb (patch) | |
| tree | 3473845b7217b48dcf43460f0a90ca655a7018ed /src/arch/arm/isa/insts/m5ops.isa | |
| parent | ade53def9252a36a39b2c4bd61196355906f0505 (diff) | |
| download | gem5-af6aaf258171027af8d3cf0ef86dddff501a3ccb.tar.xz | |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
Diffstat (limited to 'src/arch/arm/isa/insts/m5ops.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/m5ops.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index f20908d4f..222ecc647 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -247,7 +247,7 @@ let {{ m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", { "code": m5checkpoint_code, "predicate_test": predicateTest }, - ["IsNonSpeculative"]) + ["IsNonSpeculative", "IsUnverifiable"]) header_output += BasicDeclare.subst(m5checkpointIop) decoder_output += BasicConstructor.subst(m5checkpointIop) exec_output += PredOpExecute.subst(m5checkpointIop) @@ -260,7 +260,7 @@ let {{ m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", { "code": m5readfileCode, "predicate_test": predicateTest }, - ["IsNonSpeculative"]) + ["IsNonSpeculative", "IsUnverifiable"]) header_output += BasicDeclare.subst(m5readfileIop) decoder_output += BasicConstructor.subst(m5readfileIop) exec_output += PredOpExecute.subst(m5readfileIop) |