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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
commit | e097c4fb188fafc9cd2253500ab2d056da886c9c (patch) | |
tree | badbc1cc2849c52a77a211d805af04903223d469 /src/arch/arm/isa/insts/macromem.isa | |
parent | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (diff) | |
download | gem5-e097c4fb188fafc9cd2253500ab2d056da886c9c.tar.xz |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
-rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 5007c85e5..8523b840c 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -90,11 +90,10 @@ let {{ CPSR cpsr = Cpsr; SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesQ | CondCodesGE, + cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, Spsr, 0xF, true, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) @@ -635,7 +634,6 @@ let {{ NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' |