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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
| tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/macromem.isa | |
| parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
| download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz | |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 40 |
1 files changed, 24 insertions, 16 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 8523b840c..31545d3a4 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -87,15 +87,21 @@ let {{ ['IsMicroop']) microRetUopCode = ''' - CPSR cpsr = Cpsr; + CPSR old_cpsr = Cpsr; SCTLR sctlr = Sctlr; - uint32_t newCpsr = - cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE, - Spsr, 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - CondCodesF = CondCodesMaskF & newCpsr; - CondCodesGE = CondCodesMaskGE & newCpsr; - IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0); + old_cpsr.nz = CondCodesNZ; + old_cpsr.c = CondCodesC; + old_cpsr.v = CondCodesV; + old_cpsr.ge = CondCodesGE; + + CPSR new_cpsr = + cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi); + Cpsr = ~CondCodesMask & new_cpsr; + CondCodesNZ = new_cpsr.nz; + CondCodesC = new_cpsr.c; + CondCodesV = new_cpsr.v; + CondCodesGE = new_cpsr.ge; + IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0); NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC) | (((CPSR)Spsr).it1 & 0x3); SevMailbox = 1; @@ -587,7 +593,7 @@ let {{ {'code': '''URa = URb + shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -603,7 +609,7 @@ let {{ {'code': '''URa = URb - shift_rm_imm(URc, shiftAmt, shiftType, - CondCodesF<29:>); + CondCodesC); ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -625,16 +631,18 @@ let {{ CPSR cpsrOrCondCodes = URc; SCTLR sctlr = Sctlr; pNPC = URa; - uint32_t newCpsr = + CPSR new_cpsr = cpsrWriteByInstr(cpsrOrCondCodes, URb, 0xF, true, sctlr.nmfi); - Cpsr = ~CondCodesMask & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; + Cpsr = ~CondCodesMask & new_cpsr; + NextThumb = new_cpsr.t; + NextJazelle = new_cpsr.j; NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); - CondCodesF = CondCodesMaskF & newCpsr; - CondCodesGE = CondCodesMaskGE & newCpsr; + CondCodesNZ = new_cpsr.nz; + CondCodesC = new_cpsr.c; + CondCodesV = new_cpsr.v; + CondCodesGE = new_cpsr.ge; ''' microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR', |