summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/macromem.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:04 -0500
commit2419903dc0c100b1eb3111a5e0fc9b186c79e6ed (patch)
tree38609c5e76f8a81cbf0631ab9df28918f5d98bbd /src/arch/arm/isa/insts/macromem.isa
parent28227440a7645d2f486c0c1f79ef22514aeaa4c8 (diff)
downloadgem5-2419903dc0c100b1eb3111a5e0fc9b186c79e6ed.tar.xz
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
-rw-r--r--src/arch/arm/isa/insts/macromem.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 3a080625f..474e4fab0 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -66,11 +66,11 @@ let {{
['IsMicroop'])
microLdrRetUopCode = '''
- Ra = Mem;
uint32_t newCpsr =
cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
Cpsr = ~CondCodesMask & newCpsr;
CondCodes = CondCodesMask & newCpsr;
+ IWNPC = Mem | ((Spsr & 0x20) ? 1 : 0);
'''
microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
'MicroMemOp',