diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 358fdc2a40e8a455f508532b47e55f3252053805 (patch) | |
| tree | 4641a564de6d0ce42a372be77e35cde55e2c177c /src/arch/arm/isa/insts/macromem.isa | |
| parent | 596cbe19d4591b900acc022ff5a38fc7ee9a5df7 (diff) | |
| download | gem5-358fdc2a40e8a455f508532b47e55f3252053805.tar.xz | |
ARM: Decode to specialized conditional/unconditional versions of instructions.
This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 2b42dfac8..ca2c7c6ab 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -77,7 +77,7 @@ let {{ {'memacc_code': microLdrRetUopCode, 'ea_code': 'EA = Rb + (up ? imm : -imm);', - 'predicate_test': predicateTest}, + 'predicate_test': condPredicateTest}, ['IsMicroop']) microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" |