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| author | Gene WU <gene.wu@arm.com> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Gene WU <gene.wu@arm.com> | 2010-08-25 19:10:42 -0500 |
| commit | 4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe (patch) | |
| tree | dfc8029938e5580810c2a6b5cede6e72cf6f0524 /src/arch/arm/isa/insts/macromem.isa | |
| parent | c2d5d2b53d1d3bfb83ce0cf0332f81c4ffea112f (diff) | |
| download | gem5-4d8f4db8d135a23ceb5d54d3096e0598dd31e2fe.tar.xz | |
ARM: Use fewer micro-ops for register update loads if possible.
Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 38 |
1 files changed, 33 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index bcb1e26b8..f595f4043 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -575,8 +575,12 @@ let {{ ['IsMicroop']) microAddUopIop = InstObjParams('add_uop', 'MicroAddUop', - 'MicroIntOp', - {'code': 'Ra = Rb + Rc;', + 'MicroIntRegOp', + {'code': + '''Ra = Rb + shift_rm_imm(Rc, shiftAmt, + shiftType, + CondCodes<29:>); + ''', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -586,15 +590,39 @@ let {{ 'predicate_test': predicateTest}, ['IsMicroop']) + microSubUopIop = InstObjParams('sub_uop', 'MicroSubUop', + 'MicroIntRegOp', + {'code': + '''Ra = Rb - shift_rm_imm(Rc, shiftAmt, + shiftType, + CondCodes<29:>); + ''', + 'predicate_test': predicateTest}, + ['IsMicroop']) + + microUopRegMovIop = InstObjParams('uopReg_uop', 'MicroUopRegMov', + 'MicroIntMov', + {'code': 'IWRa = Rb;', + 'predicate_test': predicateTest}, + ['IsMicroop']) + header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \ MicroIntImmDeclare.subst(microSubiUopIop) + \ - MicroIntDeclare.subst(microAddUopIop) + MicroIntRegDeclare.subst(microAddUopIop) + \ + MicroIntRegDeclare.subst(microSubUopIop) + \ + MicroIntMovDeclare.subst(microUopRegMovIop) + decoder_output = MicroIntImmConstructor.subst(microAddiUopIop) + \ MicroIntImmConstructor.subst(microSubiUopIop) + \ - MicroIntConstructor.subst(microAddUopIop) + MicroIntRegConstructor.subst(microAddUopIop) + \ + MicroIntRegConstructor.subst(microSubUopIop) + \ + MicroIntMovConstructor.subst(microUopRegMovIop) + exec_output = PredOpExecute.subst(microAddiUopIop) + \ PredOpExecute.subst(microSubiUopIop) + \ - PredOpExecute.subst(microAddUopIop) + PredOpExecute.subst(microAddUopIop) + \ + PredOpExecute.subst(microSubUopIop) + \ + PredOpExecute.subst(microUopRegMovIop) }}; let {{ |