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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:52 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-03 07:42:52 -0400 |
| commit | 8f95144e161ef7bdb264eb572108a98f215785c0 (patch) | |
| tree | fed971653335ef0ee3db72d372ae3b465e10b5cd /src/arch/arm/isa/insts/macromem.isa | |
| parent | f6f63ec0aa68f631691d9eccc18739722a0a9f17 (diff) | |
| download | gem5-8f95144e161ef7bdb264eb572108a98f215785c0.tar.xz | |
arm: Make memory ops work on 64bit/128-bit quantities
Multiple instructions assume only 32-bit load operations are available,
this patch increases load sizes to 64-bit or 128-bit for many load pair and
load multiple instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index f164595dd..41060ff01 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013 ARM Limited +// Copyright (c) 2010-2014 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -55,6 +55,18 @@ let {{ 'predicate_test': predicateTest}, ['IsMicroop']) + microLdr2UopCode = ''' + uint64_t data = Mem_ud; + Dest = cSwap((uint32_t) data, ((CPSR)Cpsr).e); + Dest2 = cSwap((uint32_t) (data >> 32), ((CPSR)Cpsr).e); + ''' + microLdr2UopIop = InstObjParams('ldr2_uop', 'MicroLdr2Uop', + 'MicroMemPairOp', + {'memacc_code': microLdr2UopCode, + 'ea_code': 'EA = URb + (up ? imm : -imm);', + 'predicate_test': predicateTest}, + ['IsMicroop']) + microLdrFpUopCode = "Fa_uw = cSwap(Mem_uw, ((CPSR)Cpsr).e);" microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 'MicroMemOp', @@ -159,8 +171,8 @@ let {{ header_output = decoder_output = exec_output = '' - loadIops = (microLdrUopIop, microLdrRetUopIop, microLdrFpUopIop, - microLdrDBFpUopIop, microLdrDTFpUopIop) + loadIops = (microLdrUopIop, microLdrRetUopIop, + microLdrFpUopIop, microLdrDBFpUopIop, microLdrDTFpUopIop) storeIops = (microStrUopIop, microStrFpUopIop, microStrDBFpUopIop, microStrDTFpUopIop) for iop in loadIops + storeIops: @@ -174,6 +186,12 @@ let {{ exec_output += StoreExecute.subst(iop) + \ StoreInitiateAcc.subst(iop) + \ StoreCompleteAcc.subst(iop) + + header_output += MicroMemPairDeclare.subst(microLdr2UopIop) + decoder_output += MicroMemPairConstructor.subst(microLdr2UopIop) + exec_output += LoadExecute.subst(microLdr2UopIop) + \ + LoadInitiateAcc.subst(microLdr2UopIop) + \ + LoadCompleteAcc.subst(microLdr2UopIop) }}; let {{ |