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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:43 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-08-25 19:10:43 -0500 |
| commit | edca5f7da6bad677dfc1ea69fff904554181cc17 (patch) | |
| tree | 19e1656c6267c6677944160d10ea1a229f409b94 /src/arch/arm/isa/insts/macromem.isa | |
| parent | e6d3fe8a0c02e0692444399e63e6c5ce6c3abd17 (diff) | |
| download | gem5-edca5f7da6bad677dfc1ea69fff904554181cc17.tar.xz | |
ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
Diffstat (limited to 'src/arch/arm/isa/insts/macromem.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index f595f4043..6bf789efd 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -101,7 +101,7 @@ let {{ 'ea_code': 'EA = Rb + (up ? imm : -imm);', 'predicate_test': condPredicateTest}, - ['IsMicroop']) + ['IsMicroop','IsNonSpeculative','IsSerializeAfter']) microStrUopCode = "Mem = cSwap(Ra.uw, ((CPSR)Cpsr).e);" microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', |