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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:50 -0400 |
| commit | 3be4f4b846f991c98fe1909631996c5b58d52437 (patch) | |
| tree | d9e603e739e999def333ae04c2386af0c1dd1fdb /src/arch/arm/isa/insts/mem.isa | |
| parent | 5d029463eef3cfafa507dacadccd33402f82029a (diff) | |
| download | gem5-3be4f4b846f991c98fe1909631996c5b58d52437.tar.xz | |
mem: Fix a bug in the cache port flow control
This patch fixes a bug in the cache port where the retry flag was
reset too early, allowing new requests to arrive before the retry was
actually sent, but with the event already scheduled. This caused a
deadlock in the interactions with the O3 LSQ.
The patche fixes the underlying issue by shifting the resetting of the
flag to be done by the event that also calls sendRetry(). The patch
also tidies up the flow control in recvTimingReq and ensures that we
also check if we already have a retry outstanding.
Diffstat (limited to 'src/arch/arm/isa/insts/mem.isa')
0 files changed, 0 insertions, 0 deletions