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authorMatt Horsnell <Matt.Horsnell@arm.com>2011-03-17 19:20:19 -0500
committerMatt Horsnell <Matt.Horsnell@arm.com>2011-03-17 19:20:19 -0500
commit031f396c71e750fede19651ba3a14e262a87e117 (patch)
treebfd6520d87f36775200aff930b632bfe3c80af1e /src/arch/arm/isa/insts/mem.isa
parente65f480d62e0112e89af6130e2f2024d89417df0 (diff)
downloadgem5-031f396c71e750fede19651ba3a14e262a87e117.tar.xz
ARM: Fix RFE macrop.
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
Diffstat (limited to 'src/arch/arm/isa/insts/mem.isa')
-rw-r--r--src/arch/arm/isa/insts/mem.isa25
1 files changed, 21 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 507f8cd4b..d0c0f0710 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -48,7 +48,7 @@ let {{
self.constructTemplate = eval(self.decConstBase + 'Constructor')
def fillTemplates(self, name, Name, codeBlobs, memFlags, instFlags,
- base = 'Memory', wbDecl = None):
+ base = 'Memory', wbDecl = None, pcDecl = None):
# Make sure flags are in lists (convert to lists if not).
memFlags = makeList(memFlags)
instFlags = makeList(instFlags)
@@ -65,12 +65,26 @@ let {{
macroName = Name
instFlagsCopy = list(instFlags)
codeBlobsCopy = dict(codeBlobs)
- if wbDecl is not None:
+
+ use_uops = 0
+ if wbDecl is not None or pcDecl is not None:
instFlagsCopy.append('IsMicroop')
Name = Name + 'Acc'
+ use_uops = 1
+
+ use_wb = 0
+ use_pc = 0
+ if wbDecl is not None:
+ use_wb = 1
+ if pcDecl is not None:
+ use_pc = 1
+
codeBlobsCopy['acc_name'] = Name
codeBlobsCopy['wb_decl'] = wbDecl
+ codeBlobsCopy['pc_decl'] = pcDecl
codeBlobsCopy['use_uops'] = 0
+ codeBlobsCopy['use_wb'] = 0
+ codeBlobsCopy['use_pc'] = 0
iop = InstObjParams(name, Name, base,
codeBlobsCopy, instFlagsCopy)
@@ -81,11 +95,14 @@ let {{
self.initiateAccTemplate.subst(iop) + \
self.completeAccTemplate.subst(iop)
- if wbDecl is not None:
+ if wbDecl is not None or pcDecl is not None:
iop = InstObjParams(name, macroName, base,
{ "wb_decl" : wbDecl,
+ "pc_decl" : pcDecl,
"acc_name" : Name,
- "use_uops" : 1 },
+ "use_uops" : use_uops,
+ "use_pc" : use_pc,
+ "use_wb" : use_wb },
['IsMacroop'])
header_output += self.declareTemplate.subst(iop)
decoder_output += self.constructTemplate.subst(iop)