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author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:11 -0500 |
commit | bb6fea91da7c5436d26d6b93f22b2dd5cd6287ba (patch) | |
tree | 60685658c676826c90f3938c589880ef892a6b97 /src/arch/arm/isa/insts/mem.isa | |
parent | dbee6e0c5406200066b8185fd38fa47dae7cdd2f (diff) | |
download | gem5-bb6fea91da7c5436d26d6b93f22b2dd5cd6287ba.tar.xz |
ARM: Implement the SRS instruction.
Diffstat (limited to 'src/arch/arm/isa/insts/mem.isa')
-rw-r--r-- | src/arch/arm/isa/insts/mem.isa | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index e17235c81..51805c28e 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -38,9 +38,9 @@ // Authors: Gabe Black let {{ - def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags, - instFlags, double, strex, base = 'Memory', - execTemplateBase = ''): + def loadStoreBaseWork(name, Name, imm, swp, rfe, srs, codeBlobs, + memFlags, instFlags, double, strex, + base = 'Memory', execTemplateBase = ''): # Make sure flags are in lists (convert to lists if not). memFlags = makeList(memFlags) instFlags = makeList(instFlags) @@ -66,6 +66,9 @@ let {{ elif rfe: declareTemplate = RfeDeclare constructTemplate = RfeConstructor + elif srs: + declareTemplate = SrsDeclare + constructTemplate = SrsConstructor elif imm: if double: declareTemplate = LoadStoreDImmDeclare @@ -101,26 +104,35 @@ let {{ "memacc_code": accCode, "postacc_code": postAccCode, "predicate_test": predicateTest } - return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs, - memFlags, instFlags, double, strex, base, - execTemplateBase) + return loadStoreBaseWork(name, Name, imm, False, False, False, + codeBlobs, memFlags, instFlags, double, + strex, base, execTemplateBase) def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags): codeBlobs = { "ea_code": eaCode, "memacc_code": accCode, "predicate_test": predicateTest } - return loadStoreBaseWork(name, Name, False, False, True, codeBlobs, - memFlags, instFlags, False, False, + return loadStoreBaseWork(name, Name, False, False, True, False, + codeBlobs, memFlags, instFlags, False, False, 'RfeOp', 'Load') + def SrsBase(name, Name, eaCode, accCode, memFlags, instFlags): + codeBlobs = { "ea_code": eaCode, + "memacc_code": accCode, + "postacc_code": "", + "predicate_test": predicateTest } + return loadStoreBaseWork(name, Name, False, False, False, True, + codeBlobs, memFlags, instFlags, False, False, + 'SrsOp', 'Store') + def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags, instFlags): codeBlobs = { "ea_code": eaCode, "preacc_code": preAccCode, "postacc_code": postAccCode, "predicate_test": predicateTest } - return loadStoreBaseWork(name, Name, False, True, False, codeBlobs, - memFlags, instFlags, False, False, + return loadStoreBaseWork(name, Name, False, True, False, False, + codeBlobs, memFlags, instFlags, False, False, 'Swap', 'Swap') def memClassName(base, post, add, writeback, \ |