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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/mem.isa | |
parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/mem.isa')
-rw-r--r-- | src/arch/arm/isa/insts/mem.isa | 31 |
1 files changed, 28 insertions, 3 deletions
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 0ebd34ad4..cad0b1589 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -119,10 +119,35 @@ let {{ return (header_output, decoder_output, exec_output) def pickPredicate(blobs): + opt_nz = True + opt_c = True + opt_v = True for val in blobs.values(): - if re.search('(?<!Opt)CondCodesF', val): - return condPredicateTest - return predicateTest + if re.search('(?<!Opt)CondCodesNZ', val): + opt_nz = False + if re.search('(?<!Opt)CondCodesC', val): + opt_c = False + if re.search('(?<!Opt)CondCodesV', val): + opt_v = False + + # Build up the predicate piece by piece depending on which + # flags the instruction needs + predicate = 'testPredicate(' + if opt_nz: + predicate += 'OptCondCodesNZ, ' + else: + predicate += 'CondCodesNZ, ' + if opt_c: + predicate += 'OptCondCodesC, ' + else: + predicate += 'CondCodesC, ' + if opt_v: + predicate += 'OptCondCodesV, ' + else: + predicate += 'CondCodesV, ' + predicate += 'condCode)' + + return predicate def memClassName(base, post, add, writeback, \ size=4, sign=False, user=False): |