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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-18 01:18:46 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-20 15:33:40 +0000 |
commit | e79c4c6f033581f84072ddb45d2ec9543c31af55 (patch) | |
tree | 7c060130bd1b863ddb2b7d4a69a2d7a181885ef9 /src/arch/arm/isa/insts/misc.isa | |
parent | 4b3fee098435f1980d0d101ce5a416935d3d6a8e (diff) | |
download | gem5-e79c4c6f033581f84072ddb45d2ec9543c31af55.tar.xz |
arch-arm: RBIT instruction using mirroring func
The high speed bit-reversing function is now used
for the Aarch64/32 RBIT instruction implementation.
Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 5eda615b5..edeb0f6d3 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -329,17 +329,7 @@ let {{ exec_output += PredOpExecute.subst(revshIop) rbitCode = ''' - uint8_t *opBytes = (uint8_t *)&Op1; - uint32_t resTemp; - uint8_t *destBytes = (uint8_t *)&resTemp; - // This reverses the bytes and bits of the input, or so says the - // internet. - for (int i = 0; i < 4; i++) { - uint32_t temp = opBytes[i]; - temp = (temp * 0x0802 & 0x22110) | (temp * 0x8020 & 0x88440); - destBytes[3 - i] = (temp * 0x10101) >> 16; - } - Dest = resTemp; + Dest = reverseBits(Op1); ''' rbitIop = InstObjParams("rbit", "Rbit", "RegRegOp", { "code": rbitCode, |