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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-12-14 17:38:38 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-07 15:13:49 +0000 |
| commit | 633fdd5841d8e7798e1b1158261612a6ad84c812 (patch) | |
| tree | a572e3d8be8e82d2be24e3d1d6da54818e3e4f41 /src/arch/arm/isa/insts/misc.isa | |
| parent | 78024e6b026fecc780e503aa246beeb10dcc26d9 (diff) | |
| download | gem5-633fdd5841d8e7798e1b1158261612a6ad84c812.tar.xz | |
arch-arm: Fix AArch32 SETEND Instruction
This patch fixes AArch32 SETEND instruction, which was previously
executed unconditionally without checking (H)SCTLR.SED field. This bit
enables/disables the trapping of the instruction.
Change-Id: Ib3d2194c8d16c34ec2a9ab3e8090081900c1e42e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7981
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 5fd18c469..23962b02d 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1024,6 +1024,7 @@ let {{ CPSR cpsr = Cpsr; cpsr.e = imm; Cpsr = cpsr; + fault = checkSETENDEnabled(xc->tcBase(), cpsr); ''' setendIop = InstObjParams("setend", "Setend", "ImmOp", { "code": setendCode, |