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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:17 -0500 |
| commit | 6101e1b06276daf66e9c6c66523bb2339ccf47bf (patch) | |
| tree | fedb5dbe32948c79fd9fb0d03bf175f2c2ead089 /src/arch/arm/isa/insts/misc.isa | |
| parent | e91e6ff9a46ecee70c924e3548c3fa191e83099d (diff) | |
| download | gem5-6101e1b06276daf66e9c6c66523bb2339ccf47bf.tar.xz | |
ARM: Implement a version of mcr and mrc that works in user mode.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 7f9a5c171..6b81853f1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -614,6 +614,20 @@ let {{ decoder_output += RegRegOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) + mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc15UserIop) + decoder_output += RegRegOpConstructor.subst(mrc15UserIop) + exec_output += PredOpExecute.subst(mrc15UserIop) + + mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", + { "code": "MiscDest = Op1", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mcr15UserIop) + decoder_output += RegRegOpConstructor.subst(mcr15UserIop) + exec_output += PredOpExecute.subst(mcr15UserIop) + enterxCode = ''' FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift); ''' |