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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | a02d82f9f8cd4fb826e294bbb333ca20cb5533de (patch) | |
| tree | 69fcea93edb34bf154f92a1a86b94adeb462062d /src/arch/arm/isa/insts/misc.isa | |
| parent | d6736384b2bb280ec12d472cac6eb25a70b4af60 (diff) | |
| download | gem5-a02d82f9f8cd4fb826e294bbb333ca20cb5533de.tar.xz | |
ARM: Implement DBG instruction that doesn't do much for now.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 33197eaec..120372603 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -708,6 +708,15 @@ let {{ decoder_output += BasicConstructor.subst(dmbIop) exec_output += PredOpExecute.subst(dmbIop) + dbgCode = ''' + ''' + dbgIop = InstObjParams("dbg", "Dbg", "PredOp", + {"code": dbgCode, + "predicate_test": predicateTest}) + header_output += BasicDeclare.subst(dbgIop) + decoder_output += BasicConstructor.subst(dbgIop) + exec_output += PredOpExecute.subst(dbgIop) + cpsCode = ''' uint32_t mode = bits(imm, 4, 0); uint32_t f = bits(imm, 5); |