diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
commit | e097c4fb188fafc9cd2253500ab2d056da886c9c (patch) | |
tree | badbc1cc2849c52a77a211d805af04903223d469 /src/arch/arm/isa/insts/misc.isa | |
parent | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (diff) | |
download | gem5-e097c4fb188fafc9cd2253500ab2d056da886c9c.tar.xz |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 26 |
1 files changed, 9 insertions, 17 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index a08477703..c22384212 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -61,7 +61,7 @@ let {{ header_output = decoder_output = exec_output = "" mrsCpsrCode = ''' - Dest = (Cpsr | CondCodesF | CondCodesQ | CondCodesGE) & 0xF8FF03DF + Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF ''' mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp", @@ -84,11 +84,10 @@ let {{ msrCpsrRegCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, Op1, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -111,11 +110,10 @@ let {{ msrCpsrImmCode = ''' SCTLR sctlr = Sctlr; uint32_t newCpsr = - cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesQ | CondCodesGE, imm, + cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; CondCodesF = CondCodesMaskF & newCpsr; - CondCodesQ = CondCodesMaskQ & newCpsr; CondCodesGE = CondCodesMaskGE & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -205,9 +203,7 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (satInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp", @@ -221,9 +217,7 @@ let {{ int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0); int32_t res; if (uSatInt(res, operand, imm)) - CondCodesQ = CondCodesQ | (1 << 27); - else - CondCodesQ = CondCodesQ; + CpsrQ = 1 << 27; Dest = res; ''' usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp", @@ -236,14 +230,13 @@ let {{ ssat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (satInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (satInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' @@ -257,14 +250,13 @@ let {{ usat16Code = ''' int32_t res; uint32_t resTemp = 0; - CondCodesQ = CondCodesQ; int32_t argLow = sext<16>(bits(Op1, 15, 0)); int32_t argHigh = sext<16>(bits(Op1, 31, 16)); if (uSatInt(res, argLow, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 15, 0, res); if (uSatInt(res, argHigh, imm)) - CondCodesQ = CondCodesQ | (1 << 27); + CpsrQ = 1 << 27; replaceBits(resTemp, 31, 16, res); Dest = resTemp; ''' |