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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
commit8f566e5ee3d9e3236cced1d56c11d7f3ea4ab351 (patch)
treea38f3b2357324a8e0fd72d919fb22eb63ccced86 /src/arch/arm/isa/insts/misc.isa
parentc643b1c2749703b7823d665a7d89d0333f5c6e95 (diff)
downloadgem5-8f566e5ee3d9e3236cced1d56c11d7f3ea4ab351.tar.xz
ARM: Implement the usad8 and usada8 instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
-rw-r--r--src/arch/arm/isa/insts/misc.isa36
1 files changed, 36 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 015f93805..00780d9c9 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -387,4 +387,40 @@ let {{
header_output += RegRegRegOpDeclare.subst(selIop)
decoder_output += RegRegRegOpConstructor.subst(selIop)
exec_output += PredOpExecute.subst(selIop)
+
+ usad8Code = '''
+ uint32_t resTemp = 0;
+ for (unsigned i = 0; i < 4; i++) {
+ int low = i * 8;
+ int high = low + 7;
+ int32_t diff = bits(Op1, high, low) -
+ bits(Op2, high, low);
+ resTemp += ((diff < 0) ? -diff : diff);
+ }
+ Dest = resTemp;
+ '''
+ usad8Iop = InstObjParams("usad8", "Usad8", "RegRegRegOp",
+ { "code": usad8Code,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegRegOpDeclare.subst(usad8Iop)
+ decoder_output += RegRegRegOpConstructor.subst(usad8Iop)
+ exec_output += PredOpExecute.subst(usad8Iop)
+
+ usada8Code = '''
+ uint32_t resTemp = 0;
+ for (unsigned i = 0; i < 4; i++) {
+ int low = i * 8;
+ int high = low + 7;
+ int32_t diff = bits(Op1, high, low) -
+ bits(Op2, high, low);
+ resTemp += ((diff < 0) ? -diff : diff);
+ }
+ Dest = Op3 + resTemp;
+ '''
+ usada8Iop = InstObjParams("usada8", "Usada8", "RegRegRegRegOp",
+ { "code": usada8Code,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegRegRegOpDeclare.subst(usada8Iop)
+ decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
+ exec_output += PredOpExecute.subst(usada8Iop)
}};