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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | d6736384b2bb280ec12d472cac6eb25a70b4af60 (patch) | |
| tree | 4ab72a9724a1f349a6c9ddc3088e73d7cebd7f90 /src/arch/arm/isa/insts/misc.isa | |
| parent | 23626d99af9469b5a86f510e0542846f5af65cbd (diff) | |
| download | gem5-d6736384b2bb280ec12d472cac6eb25a70b4af60.tar.xz | |
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 2228a0f24..33197eaec 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -669,7 +669,7 @@ let {{ exec_output += PredOpExecute.subst(setendIop) clrexCode = ''' - unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC; + unsigned memAccessFlags = Request::CLREX|3|Request::LLSC; fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); ''' clrexIop = InstObjParams("clrex", "Clrex","PredOp", |