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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (patch) | |
| tree | 58d50fab58de1e9165bfc28986913811b26b9568 /src/arch/arm/isa/insts/misc.isa | |
| parent | b93ceef5381b7c84b6887b5299ae81ff48ef45c9 (diff) | |
| download | gem5-05bd3eb4ec3d9fea3dbc46112a47459085d3011c.tar.xz | |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 722b05eac..ee6330f48 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -456,10 +456,18 @@ let {{ decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) exec_output += PredOpExecute.subst(usada8Iop) - nopIop = InstObjParams("nop", "NopInst", "ArmStaticInst", "", []) + nopIop = InstObjParams("nop", "NopInst", "PredOp", \ + { "code" : "", "predicate_test" : predicateTest }) header_output += BasicDeclare.subst(nopIop) decoder_output += BasicConstructor.subst(nopIop) - exec_output += BasicExecute.subst(nopIop) + exec_output += PredOpExecute.subst(nopIop) + + itIop = InstObjParams("it", "ItInst", "PredOp", \ + { "code" : "Itstate = machInst.newItstate;", + "predicate_test" : predicateTest }) + header_output += BasicDeclare.subst(itIop) + decoder_output += BasicConstructor.subst(itIop) + exec_output += PredOpExecute.subst(itIop) ubfxCode = ''' Dest = bits(Op1, imm2, imm1); |