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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-27 09:08:37 -0400 |
| commit | ec41000dadd5256fd90f0bfdc97264946e50a3aa (patch) | |
| tree | b045e00e601839d4f49cb85321b544b71341abce /src/arch/arm/isa/insts/misc.isa | |
| parent | 341dbf266258dcbdb1e5e9f09c244b8ac271faaf (diff) | |
| download | gem5-ec41000dadd5256fd90f0bfdc97264946e50a3aa.tar.xz | |
arm: Fixed undefined behaviours identified by gcc
This patch fixes the runtime errors highlighted by the undefined
behaviour sanitizer. In the end there were two issues. First, when
rotating an immediate, we ended up shifting an uint32_t by 32 in some
cases. This case is fixed by checking for a rotation by 0
positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and
a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex
as an IntRegIndex. This issue is resolved by introducing a
MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types.
With these fixes there are no runtime errors identified for the full
ARM regressions.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 76fc1fbed..00c907acd 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -860,11 +860,11 @@ let {{ Dest = MiscNsBankedOp1; ''' - mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegImmOp", + mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", { "code": mrc15code, "predicate_test": predicateTest }, []) - header_output += RegRegImmOpDeclare.subst(mrc15Iop) - decoder_output += RegRegImmOpConstructor.subst(mrc15Iop) + header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) + decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) exec_output += PredOpExecute.subst(mrc15Iop) @@ -887,12 +887,12 @@ let {{ } MiscNsBankedDest = Op1; ''' - mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegImmOp", + mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", { "code": mcr15code, "predicate_test": predicateTest }, ["IsSerializeAfter","IsNonSpeculative"]) - header_output += RegRegImmOpDeclare.subst(mcr15Iop) - decoder_output += RegRegImmOpConstructor.subst(mcr15Iop) + header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) + decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) |