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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 4683cd165575d6e1c5a309f10a96f4d592d7a386 (patch) | |
| tree | 25ea874ab9c9aa9d487acd673501a47356d7b577 /src/arch/arm/isa/insts/misc.isa | |
| parent | fb2329791464a3ea9d8c13a6aa17bf9e379dbdb9 (diff) | |
| download | gem5-4683cd165575d6e1c5a309f10a96f4d592d7a386.tar.xz | |
ARM: Define the setend instruction.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 7ec18c9e9..c7caf5cb7 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -534,4 +534,16 @@ let {{ header_output += BasicDeclare.subst(leavexIop) decoder_output += BasicConstructor.subst(leavexIop) exec_output += PredOpExecute.subst(leavexIop) + + setendCode = ''' + CPSR cpsr = Cpsr; + cpsr.e = imm; + Cpsr = cpsr; + ''' + setendIop = InstObjParams("setend", "Setend", "ImmOp", + { "code": setendCode, + "predicate_test": predicateTest }, []) + header_output += ImmOpDeclare.subst(setendIop) + decoder_output += ImmOpConstructor.subst(setendIop) + exec_output += PredOpExecute.subst(setendIop) }}; |