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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-28 11:20:11 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-10 17:12:37 +0000 |
| commit | 7d507b72a852bbab93742bf767b600c9d4f89b4e (patch) | |
| tree | cd8bd81657812ac2f8a96899377d5749d2fe16c5 /src/arch/arm/isa/insts/misc.isa | |
| parent | 421c2e2b2186551cd9310b30d26a4805dfa0482e (diff) | |
| download | gem5-7d507b72a852bbab93742bf767b600c9d4f89b4e.tar.xz | |
arch-arm: Fix mrc,mcr to cop14 disassemble
This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions.
Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9681
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 3aeee0456..f1c6acff3 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -875,11 +875,11 @@ let {{ Dest = MiscOp1; ''' - mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp", + mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp", { "code": mrc14code, "predicate_test": predicateTest }, []) - header_output += RegRegImmOpDeclare.subst(mrc14Iop) - decoder_output += RegRegImmOpConstructor.subst(mrc14Iop) + header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop) + decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop) exec_output += PredOpExecute.subst(mrc14Iop) @@ -899,12 +899,12 @@ let {{ } MiscDest = Op1; ''' - mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp", + mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp", { "code": mcr14code, "predicate_test": predicateTest }, ["IsSerializeAfter","IsNonSpeculative"]) - header_output += RegRegImmOpDeclare.subst(mcr14Iop) - decoder_output += RegRegImmOpConstructor.subst(mcr14Iop) + header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop) + decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop) exec_output += PredOpExecute.subst(mcr14Iop) mrc15code = ''' |