diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | a679cd917ac4775979e23594de52f1bca407c08c (patch) | |
| tree | d48bb74b729d2e11e62e1db9a4fb860b70ddd1b3 /src/arch/arm/isa/insts/misc.isa | |
| parent | ac650199eeb62bf05fec11a4f2d7666cbd31331c (diff) | |
| download | gem5-a679cd917ac4775979e23594de52f1bca407c08c.tar.xz | |
ARM: Cleanup implementation of ITSTATE and put important code in PCState.
Consolidate all code to handle ITSTATE in the PCState object rather than
touching a variety of structures/objects.
Diffstat (limited to 'src/arch/arm/isa/insts/misc.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index cf5c7b47a..35df88c81 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -83,10 +83,6 @@ let {{ uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; - ForcedItState = ((((CPSR)Op1).it2 << 2) & 0xFC) - | (((CPSR)Op1).it1 & 0x3); CondCodes = CondCodesMask & newCpsr; ''' msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp", @@ -111,10 +107,6 @@ let {{ uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi); Cpsr = ~CondCodesMask & newCpsr; - NextThumb = ((CPSR)newCpsr).t; - NextJazelle = ((CPSR)newCpsr).j; - ForcedItState = ((((CPSR)imm).it2 << 2) & 0xFC) - | (((CPSR)imm).it1 & 0x3); CondCodes = CondCodesMask & newCpsr; ''' msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp", @@ -538,7 +530,7 @@ let {{ exec_output += PredOpExecute.subst(sevIop) itIop = InstObjParams("it", "ItInst", "PredOp", \ - { "code" : "Itstate = machInst.newItstate;", + { "code" : ";", "predicate_test" : predicateTest }, ["IsNonSpeculative", "IsSerializeAfter"]) header_output += BasicDeclare.subst(itIop) |