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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-15 09:55:20 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:30:02 +0000 |
| commit | 38a1e23c3910aa10c41478ba1715f50c4b4a8ac2 (patch) | |
| tree | f3b78e8a49fb46e1b99246cc8976c08382804215 /src/arch/arm/isa/insts/misc64.isa | |
| parent | 73dcf05f633b5e3a7d9a16338a64c1832ef38388 (diff) | |
| download | gem5-38a1e23c3910aa10c41478ba1715f50c4b4a8ac2.tar.xz | |
arch-arm: Make hlt64 a mem barrier with semihosting
The HLT instruction is used to trap into semihosting. The semihosting
code can change the contents of memory behind the back of the CPU,
which requires instructions triggering semihosting to be
non-speculative and memory barriers.
Change-Id: I735166251aa194120ad49c08082d4ac65fe96524
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8373
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/misc64.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/misc64.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 17d8df10d..2621905c7 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -191,6 +191,6 @@ let {{ hltIop = InstObjParams("hlt", "Hlt64", "ImmOp64", hltCode, ["IsNonSpeculative"]) header_output += ImmOp64Declare.subst(hltIop) - decoder_output += ImmOp64Constructor.subst(hltIop) + decoder_output += SemihostConstructor64.subst(hltIop) exec_output += BasicExecute.subst(hltIop) }}; |