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authorDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:02 +0100
committerDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:02 +0100
commit2950a95672599a9baf9007c18faf210ff9c3e392 (patch)
treeca19e4c650f16aad2a0a377b72ae287e248b5250 /src/arch/arm/isa/insts/misc64.isa
parentc53a57f74f31c2593665bae716c5c3679aab5595 (diff)
downloadgem5-2950a95672599a9baf9007c18faf210ff9c3e392.tar.xz
arm: Add AArch64 hypervisor call instruction 'hvc'
This patch adds the AArch64 instruction hvc which raises an exception from EL1 into EL2. The host OS uses this instruction to world switch into the guest. Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
Diffstat (limited to 'src/arch/arm/isa/insts/misc64.isa')
-rw-r--r--src/arch/arm/isa/insts/misc64.isa20
1 files changed, 19 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 7e88bebbb..08902abe8 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2013 ARM Limited
+// Copyright (c) 2011-2013, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -49,6 +49,24 @@ let {{
decoder_output = BasicConstructor64.subst(svcIop)
exec_output = BasicExecute.subst(svcIop)
+ hvcCode = '''
+ SCR scr = Scr64;
+
+ if (!ArmSystem::haveVirtualization(xc->tcBase()) ||
+ (ArmSystem::haveSecurity(xc->tcBase()) && !scr.hce)) {
+ fault = disabledFault();
+ } else {
+ fault = std::make_shared<HypervisorCall>(machInst, bits(machInst, 20, 5));
+ }
+ '''
+
+ hvcIop = InstObjParams("hvc", "Hvc64", "ArmStaticInst",
+ hvcCode, ["IsSyscall", "IsNonSpeculative",
+ "IsSerializeAfter"])
+ header_output += BasicDeclare.subst(hvcIop)
+ decoder_output += BasicConstructor64.subst(hvcIop)
+ exec_output += BasicExecute.subst(hvcIop)
+
# @todo: extend to take into account Virtualization.
smcCode = '''
SCR scr = Scr64;