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| author | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
|---|---|---|
| committer | Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> | 2010-11-15 14:04:04 -0600 |
| commit | 005892719047c3b4b383d9aeeeb481039518f661 (patch) | |
| tree | b2d967a9ffea13f73e092804ae141d9520ff109c /src/arch/arm/isa/insts/mult.isa | |
| parent | 2a3cefe15115a094eadd74a659a2f919a83ac6a4 (diff) | |
| download | gem5-005892719047c3b4b383d9aeeeb481039518f661.tar.xz | |
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Diffstat (limited to 'src/arch/arm/isa/insts/mult.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/mult.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa index ffe59117b..ae8f04a81 100644 --- a/src/arch/arm/isa/insts/mult.isa +++ b/src/arch/arm/isa/insts/mult.isa @@ -88,11 +88,13 @@ let {{ if unCc: iop = InstObjParams(mnem, Name, base, {"code" : code, - "predicate_test": predicateTest}) + "predicate_test": predicateTest, + "op_class": "IntMultOp" }) if doCc: iopCc = InstObjParams(mnem + "s", Name + "Cc", base, {"code" : code + ccCode, - "predicate_test": condPredicateTest}) + "predicate_test": condPredicateTest, + "op_class": "IntMultOp" }) if regs == 3: declare = Mult3Declare |