diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:10:34 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:10:34 -0800 |
| commit | 36a822f08e88483b41af214ace4fd3dccf3aa8cb (patch) | |
| tree | d7c4c08590459d967a1d7638b02c586911826953 /src/arch/arm/isa/insts/neon.isa | |
| parent | 85424bef192c02a47c0d46c2d99ac0a5d6e55a99 (diff) | |
| parent | f171a29118e1d80c04c72d2fb5f024fed4fb62af (diff) | |
| download | gem5-36a822f08e88483b41af214ace4fd3dccf3aa8cb.tar.xz | |
Merge with main repository.
Diffstat (limited to 'src/arch/arm/isa/insts/neon.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 9565ee14a..b1ad1eeb3 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1616,10 +1616,8 @@ let {{ threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) - threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes, + threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 2, vaddCode, pairwise=True) - threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes, - 4, vaddCode, pairwise=True) vaddlwCode = ''' destElem = (BigElement)srcElem1 + (BigElement)srcElem2; ''' @@ -2110,11 +2108,9 @@ let {{ ''' threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) - threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True) + threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True) + threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) vqdmulhCode = ''' FPSCR fpscr = (FPSCR) FpscrQc; @@ -3137,8 +3133,10 @@ let {{ destReg.elements[i + 1] = mid; } ''' - twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode) - twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", + smallUnsignedTypes, 2, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", + smallUnsignedTypes, 4, vtrnCode) vuzpCode = ''' Element mid[eCount]; |