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authorGabe Black <gabeblack@google.com>2018-10-12 23:32:43 -0700
committerGabe Black <gabeblack@google.com>2019-01-14 21:29:28 +0000
commitd4116b03ade72c8f0e73098d8a3f8563188717ac (patch)
tree6717f15d1756e0a71d744363619c8c3327cd80cb /src/arch/arm/isa/insts/neon64.isa
parentfd834ffb5334689792c81970c8da26ce27182932 (diff)
downloadgem5-d4116b03ade72c8f0e73098d8a3f8563188717ac.tar.xz
arm: Stop using the FloatReg and FloatRegBits types.
This will let us make those types 64 bits to be in line with the other architectures. Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021 Reviewed-on: https://gem5-review.googlesource.com/c/13621 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts/neon64.isa')
-rw-r--r--src/arch/arm/isa/insts/neon64.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index eb130dbbd..855952d9e 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -828,13 +828,13 @@ let {{
union
{
uint8_t bytes[64];
- FloatRegBits regs[16];
+ uint32_t regs[16];
} table;
union
{
uint8_t bytes[%(rCount)d * 4];
- FloatRegBits regs[%(rCount)d];
+ uint32_t regs[%(rCount)d];
} destReg, srcReg2;
const unsigned length = %(length)d;