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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:01 -0500
commit3b93015304382f669a74ba21d65588a1d2235468 (patch)
treea117a545694f6ba4b115afe79a3fc9faccc9cfbe /src/arch/arm/isa/insts/str.isa
parent81fdced83f21db2fc1da1541365166fbd5918027 (diff)
downloadgem5-3b93015304382f669a74ba21d65588a1d2235468.tar.xz
ARM: Define the store instructions from outside the decoder.
--HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
Diffstat (limited to 'src/arch/arm/isa/insts/str.isa')
-rw-r--r--src/arch/arm/isa/insts/str.isa139
1 files changed, 139 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
new file mode 100644
index 000000000..a051b0e72
--- /dev/null
+++ b/src/arch/arm/isa/insts/str.isa
@@ -0,0 +1,139 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+let {{
+
+ header_output = ""
+ decoder_output = ""
+ exec_output = ""
+
+ def storeImmClassName(post, add, writeback, \
+ size=4, sign=False, user=False):
+ return memClassName("STORE_IMM", post, add, writeback,
+ size, sign, user)
+
+ def storeRegClassName(post, add, writeback, \
+ size=4, sign=False, user=False):
+ return memClassName("STORE_REG", post, add, writeback,
+ size, sign, user)
+
+ def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
+ global header_output, decoder_output, exec_output
+
+ (newHeader,
+ newDecoder,
+ newExec) = newLoadStoreBase(name, Name, imm,
+ eaCode, accCode,
+ memFlags, instFlags,
+ base, execTemplateBase = 'Store')
+
+ header_output += newHeader
+ decoder_output += newDecoder
+ exec_output += newExec
+
+ def buildImmStore(mnem, post, add, writeback, \
+ size=4, sign=False, user=False):
+ name = mnem
+ Name = storeImmClassName(post, add, writeback, \
+ size, sign, user)
+
+ if add:
+ op = " +"
+ else:
+ op = " -"
+
+ offset = op + " imm"
+ eaCode = "EA = Base"
+ if not post:
+ eaCode += offset
+ eaCode += ";"
+
+ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ if writeback:
+ accCode += "Base = Base %s;\n" % offset
+ base = buildMemBase("MemoryNewImm", post, writeback)
+
+ emitStore(name, Name, True, eaCode, accCode, [], [], base)
+
+ def buildRegStore(mnem, post, add, writeback, \
+ size=4, sign=False, user=False):
+ name = mnem
+ Name = storeRegClassName(post, add, writeback,
+ size, sign, user)
+
+ if add:
+ op = " +"
+ else:
+ op = " -"
+
+ offset = op + " shift_rm_imm(Index, shiftAmt," + \
+ " shiftType, CondCodes<29:>)"
+ eaCode = "EA = Base"
+ if not post:
+ eaCode += offset
+ eaCode += ";"
+
+ accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
+ if writeback:
+ accCode += "Base = Base %s;\n" % offset
+ base = buildMemBase("MemoryNewReg", post, writeback)
+
+ emitStore(name, Name, False, eaCode, accCode, [], [], base)
+
+ def buildStores(mnem, size=4, sign=False, user=False):
+ buildImmStore(mnem, True, True, True, size, sign, user)
+ buildRegStore(mnem, True, True, True, size, sign, user)
+ buildImmStore(mnem, True, False, True, size, sign, user)
+ buildRegStore(mnem, True, False, True, size, sign, user)
+ buildImmStore(mnem, False, True, True, size, sign, user)
+ buildRegStore(mnem, False, True, True, size, sign, user)
+ buildImmStore(mnem, False, False, True, size, sign, user)
+ buildRegStore(mnem, False, False, True, size, sign, user)
+ buildImmStore(mnem, False, True, False, size, sign, user)
+ buildRegStore(mnem, False, True, False, size, sign, user)
+ buildImmStore(mnem, False, False, False, size, sign, user)
+ buildRegStore(mnem, False, False, False, size, sign, user)
+
+ buildStores("str")
+ buildStores("strt", user=True)
+ buildStores("strb", size=1)
+ buildStores("strbt", size=1, user=True)
+ buildStores("strh", size=2)
+ buildStores("strht", size=2, user=True)
+}};