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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 1d5233958ad208e3b229e394ba5ab689b82d8cac (patch) | |
| tree | de69dd4bac297c10f9e6355b06b5e1f5f12c9e90 /src/arch/arm/isa/insts/str.isa | |
| parent | 7b397925af7fd9864189387179137dd4ac40dfad (diff) | |
| download | gem5-1d5233958ad208e3b229e394ba5ab689b82d8cac.tar.xz | |
ARM: Implement the V7 version of alignment checking.
Diffstat (limited to 'src/arch/arm/isa/insts/str.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/str.isa | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index cf9eed74e..c22245947 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -98,7 +98,10 @@ let {{ accCode += "Base = Base %s;\n" % offset base = buildMemBase("MemoryImm", post, writeback) - emitStore(name, Name, True, eaCode, accCode, [], [], base) + emitStore(name, Name, True, eaCode, accCode, \ + ["ArmISA::TLB::MustBeOne", \ + "ArmISA::TLB::AllowUnaligned", \ + "%d" % (size - 1)], [], base) def buildRegStore(mnem, post, add, writeback, \ size=4, sign=False, user=False): @@ -123,7 +126,10 @@ let {{ accCode += "Base = Base %s;\n" % offset base = buildMemBase("MemoryReg", post, writeback) - emitStore(name, Name, False, eaCode, accCode, [], [], base) + emitStore(name, Name, False, eaCode, accCode, \ + ["ArmISA::TLB::MustBeOne", \ + "ArmISA::TLB::AllowUnaligned", \ + "%d" % (size - 1)], [], base) def buildDoubleImmStore(mnem, post, add, writeback): name = mnem @@ -146,7 +152,8 @@ let {{ base = buildMemBase("MemoryDImm", post, writeback) emitStore(name, Name, True, eaCode, accCode, \ - [], [], base, double=True) + ["ArmISA::TLB::MustBeOne", + "ArmISA::TLB::AlignWord"], [], base, double=True) def buildDoubleRegStore(mnem, post, add, writeback): name = mnem @@ -170,7 +177,8 @@ let {{ base = buildMemBase("MemoryDReg", post, writeback) emitStore(name, Name, False, eaCode, accCode, \ - [], [], base, double=True) + ["ArmISA::TLB::MustBeOne", \ + "ArmISA::TLB::AlignWord"], [], base, double=True) def buildStores(mnem, size=4, sign=False, user=False): buildImmStore(mnem, True, True, True, size, sign, user) |