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author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
commit | 401165c778108ab22aeeee55c4f4451ca93bcffb (patch) | |
tree | f525ba64108f6ebe208a04d2dee7b77621cafd96 /src/arch/arm/isa/insts/str.isa | |
parent | e097c4fb188fafc9cd2253500ab2d056da886c9c (diff) | |
download | gem5-401165c778108ab22aeeee55c4f4451ca93bcffb.tar.xz |
ARM: Further break up condition code into NZ, C, V bits.
Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
Diffstat (limited to 'src/arch/arm/isa/insts/str.isa')
-rw-r--r-- | src/arch/arm/isa/insts/str.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index 312bcac16..95ba4ad39 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -152,7 +152,7 @@ let {{ def __init__(self, *args, **kargs): super(StoreRegInst, self).__init__(*args, **kargs) self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \ - " shiftType, CondCodesF<29:>)" + " shiftType, CondCodesC)" if self.add: self.wbDecl = ''' MicroAddUop(machInst, base, base, index, shiftAmt, shiftType); |