diff options
| author | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
|---|---|---|
| committer | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
| commit | 8870a5820a458ca22cbd4bec60f223a4fe4949e6 (patch) | |
| tree | d0407f485a0bd6c861dd09f86e5a494dc26ed04d /src/arch/arm/isa/insts/swap.isa | |
| parent | e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1 (diff) | |
| download | gem5-8870a5820a458ca22cbd4bec60f223a4fe4949e6.tar.xz | |
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index 6a6ac837c..3be4278fa 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -71,8 +71,18 @@ let {{ decoder_output += newDecoder exec_output += newExec + swpPreAccCode = ''' + if (!((SCTLR)Sctlr).sw) { +#if FULL_SYSTEM + return new UndefinedInstruction; +#else + return new UndefinedInstruction(false, mnemonic); +#endif + } + ''' + SwapInst('swp', 'Swp', 'EA = Base;', - 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem = cSwap(Op1.uw, ((CPSR)Cpsr).e);', 'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignWord', @@ -80,7 +90,7 @@ let {{ ['IsStoreConditional']).emit() SwapInst('swpb', 'Swpb', 'EA = Base;', - 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', + swpPreAccCode + 'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);', 'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);', ['Request::MEM_SWAP', 'ArmISA::TLB::AlignByte', |