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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:10 -0500 |
| commit | 1d5233958ad208e3b229e394ba5ab689b82d8cac (patch) | |
| tree | de69dd4bac297c10f9e6355b06b5e1f5f12c9e90 /src/arch/arm/isa/insts/swap.isa | |
| parent | 7b397925af7fd9864189387179137dd4ac40dfad (diff) | |
| download | gem5-1d5233958ad208e3b229e394ba5ab689b82d8cac.tar.xz | |
ARM: Implement the V7 version of alignment checking.
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index 6cbca6d6c..9456c1314 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -45,7 +45,9 @@ let {{ newDecoder, newExec) = SwapBase("swp", "Swp", "EA = Base;", "Mem = Op1;", "Dest = memData;", - ["Request::MEM_SWAP"], []) + ["Request::MEM_SWAP", + "ArmISA::TLB::AlignWord", + "ArmISA::TLB::MustBeOne"], []) header_output += newHeader decoder_output += newDecoder exec_output += newExec @@ -54,7 +56,9 @@ let {{ newDecoder, newExec) = SwapBase("swpb", "Swpb", "EA = Base;", "Mem.ub = Op1.ub;", "Dest.ub = (uint8_t)memData;", - ["Request::MEM_SWAP"], []) + ["Request::MEM_SWAP", + "ArmISA::TLB::AlignByte", + "ArmISA::TLB::MustBeOne"], []) header_output += newHeader decoder_output += newDecoder exec_output += newExec |