diff options
| author | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-12-07 16:19:57 -0800 |
|---|---|---|
| committer | Min Kyu Jeong <minkyu.jeong@arm.com> | 2010-12-07 16:19:57 -0800 |
| commit | 4bbdd6ceb2639fe21408ab211b7c4c7e53adb249 (patch) | |
| tree | b2fb062d30bc3b091d4390a671a2b0268e166121 /src/arch/arm/isa/insts/swap.isa | |
| parent | 21bfbd422cb9d043f88bd7f5ca9d4c72b97f9f33 (diff) | |
| download | gem5-4bbdd6ceb2639fe21408ab211b7c4c7e53adb249.tar.xz | |
O3: Support SWAP and predicated loads/store in ARM.
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
| -rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index c5c92c935..d924f3029 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -65,7 +65,9 @@ let {{ (newHeader, newDecoder, newExec) = self.fillTemplates(self.name, self.Name, codeBlobs, - self.memFlags, [], base = 'Swap') + self.memFlags, + ['IsStoreConditional'], + base = 'Swap') header_output += newHeader decoder_output += newDecoder exec_output += newExec |