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| author | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
|---|---|---|
| committer | Wade Walker <wade.walker@arm.com> | 2011-07-15 11:53:34 -0500 |
| commit | e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1 (patch) | |
| tree | 2195fa893b9bcdcfe13db3e16d2f140b84e33d61 /src/arch/arm/isa/insts/swap.isa | |
| parent | d919930c3c7f5d364f211513742a51f56e36eaab (diff) | |
| download | gem5-e6672d1f291e415c6d7e0453dabe8c8b7eb5ddc1.tar.xz | |
ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
Diffstat (limited to 'src/arch/arm/isa/insts/swap.isa')
0 files changed, 0 insertions, 0 deletions