ARM: Explicitly keep track of the second destination for double loads/stores.

3 files changed, 44 insertions, 27 deletions

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index da20cab0b..6b8c925b6 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -59,14 +59,15 @@ let {{
     def loadDoubleRegClassName(post, add, writeback):
         return memClassName("LOAD_REGD", post, add, writeback, 4, False, False)
 
-    def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
+    def emitLoad(name, Name, imm, eaCode, accCode, \
+                 memFlags, instFlags, base, double=False):
         global header_output, decoder_output, exec_output
 
         (newHeader,
          newDecoder,
          newExec) = loadStoreBase(name, Name, imm,
                                   eaCode, accCode,
-                                  memFlags, instFlags,
+                                  memFlags, instFlags, double,
                                   base, execTemplateBase = 'Load')
 
         header_output += newHeader
@@ -143,7 +144,8 @@ let {{
             accCode += "Base = Base %s;\n" % offset
         base = buildMemBase("MemoryReg", post, writeback)
 
-        emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
+        emitLoad(name, Name, False, eaCode, accCode, \
+                 memFlags, [], base)
 
     def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False):
         name = mnem
@@ -161,8 +163,8 @@ let {{
         eaCode += ";"
 
         accCode = '''
-        Rdo = bits(Mem.ud, 31, 0);
-        Rde = bits(Mem.ud, 63, 32);
+        Dest = bits(Mem.ud, 31, 0);
+        Dest2 = bits(Mem.ud, 63, 32);
         '''
         if ldrex:
             memFlags = ["Request::LLSC"]
@@ -171,9 +173,10 @@ let {{
             memFlags = []
         if writeback:
             accCode += "Base = Base %s;\n" % offset
-        base = buildMemBase("MemoryImm", post, writeback)
+        base = buildMemBase("MemoryDImm", post, writeback)
 
-        emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
+        emitLoad(name, Name, True, eaCode, accCode, \
+                 memFlags, [], base, double=True)
 
     def buildDoubleRegLoad(mnem, post, add, writeback):
         name = mnem
@@ -192,14 +195,15 @@ let {{
         eaCode += ";"
 
         accCode = '''
-        Rdo = bits(Mem.ud, 31, 0);
-        Rde = bits(Mem.ud, 63, 32);
+        Dest = bits(Mem.ud, 31, 0);
+        Dest2 = bits(Mem.ud, 63, 32);
         '''
         if writeback:
             accCode += "Base = Base %s;\n" % offset
-        base = buildMemBase("MemoryReg", post, writeback)
+        base = buildMemBase("MemoryDReg", post, writeback)
 
-        emitLoad(name, Name, False, eaCode, accCode, [], [], base)
+        emitLoad(name, Name, False, eaCode, accCode,
+                 [], [], base, double=True)
 
     def buildLoads(mnem, size=4, sign=False, user=False):
         buildImmLoad(mnem, True, True, True, size, sign, user)
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 21687b225..dc447cf8b 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -39,7 +39,8 @@
 
 let {{
     def loadStoreBaseWork(name, Name, imm, swp, codeBlobs, memFlags,
-                          instFlags, base = 'Memory', execTemplateBase = ''):
+                          instFlags, double, base = 'Memory',
+                          execTemplateBase = ''):
         # Make sure flags are in lists (convert to lists if not).
         memFlags = makeList(memFlags)
         instFlags = makeList(instFlags)
@@ -66,11 +67,19 @@ let {{
             declareTemplate = SwapDeclare
             constructTemplate = SwapConstructor
         elif imm:
-            declareTemplate = LoadStoreImmDeclare
-            constructTemplate = LoadStoreImmConstructor
+            if double:
+                declareTemplate = LoadStoreDImmDeclare
+                constructTemplate = LoadStoreDImmConstructor
+            else:
+                declareTemplate = LoadStoreImmDeclare
+                constructTemplate = LoadStoreImmConstructor
         else:
-            declareTemplate = LoadStoreRegDeclare
-            constructTemplate = LoadStoreRegConstructor
+            if double:
+                declareTemplate = LoadStoreDRegDeclare
+                constructTemplate = LoadStoreDRegConstructor
+            else:
+                declareTemplate = LoadStoreRegDeclare
+                constructTemplate = LoadStoreRegConstructor
 
         # (header_output, decoder_output, decode_block, exec_output)
         return (declareTemplate.subst(iop),
@@ -80,12 +89,13 @@ let {{
                 + completeAccTemplate.subst(iop))
 
     def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
-                      instFlags, base = 'Memory', execTemplateBase = ''):
+                      instFlags, double, base = 'Memory',
+                      execTemplateBase = ''):
         codeBlobs = { "ea_code": eaCode,
                       "memacc_code": accCode,
                       "predicate_test": predicateTest }
         return loadStoreBaseWork(name, Name, imm, False, codeBlobs, memFlags,
-                                 instFlags, base, execTemplateBase)
+                                 instFlags, double, base, execTemplateBase)
 
     def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags,
                  instFlags):
@@ -94,7 +104,7 @@ let {{
                       "postacc_code": postAccCode,
                       "predicate_test": predicateTest }
         return loadStoreBaseWork(name, Name, False, True, codeBlobs, memFlags,
-                                 instFlags, 'Swap', 'Swap')
+                                 instFlags, False, 'Swap', 'Swap')
 
     def memClassName(base, post, add, writeback, \
                      size=4, sign=False, user=False):
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 3349ba029..cf9eed74e 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -61,14 +61,15 @@ let {{
         return memClassName("STORE_REGD", post, add, writeback,
                             4, False, False)
 
-    def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
+    def emitStore(name, Name, imm, eaCode, accCode, \
+                  memFlags, instFlags, base, double=False):
         global header_output, decoder_output, exec_output
 
         (newHeader,
          newDecoder,
          newExec) = loadStoreBase(name, Name, imm,
                                   eaCode, accCode,
-                                  memFlags, instFlags,
+                                  memFlags, instFlags, double,
                                   base, execTemplateBase = 'Store')
 
         header_output += newHeader
@@ -139,12 +140,13 @@ let {{
             eaCode += offset
         eaCode += ";"
 
-        accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
+        accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
         if writeback:
             accCode += "Base = Base %s;\n" % offset
-        base = buildMemBase("MemoryImm", post, writeback)
+        base = buildMemBase("MemoryDImm", post, writeback)
 
-        emitStore(name, Name, True, eaCode, accCode, [], [], base)
+        emitStore(name, Name, True, eaCode, accCode, \
+                  [], [], base, double=True)
 
     def buildDoubleRegStore(mnem, post, add, writeback):
         name = mnem
@@ -162,12 +164,13 @@ let {{
             eaCode += offset
         eaCode += ";"
 
-        accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);'
+        accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);'
         if writeback:
             accCode += "Base = Base %s;\n" % offset
-        base = buildMemBase("MemoryReg", post, writeback)
+        base = buildMemBase("MemoryDReg", post, writeback)
 
-        emitStore(name, Name, False, eaCode, accCode, [], [], base)
+        emitStore(name, Name, False, eaCode, accCode, \
+                  [], [], base, double=True)
 
     def buildStores(mnem, size=4, sign=False, user=False):
         buildImmStore(mnem, True, True, True, size, sign, user)