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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commit1f032ad3452c2514287c142fb3faf953a5682ea3 (patch)
treec37398638ecd1fcc43cb22c9c87f0384d7928127 /src/arch/arm/isa/insts
parent66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (diff)
downloadgem5-1f032ad3452c2514287c142fb3faf953a5682ea3.tar.xz
ARM: Implement CLREX
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/misc.isa11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 341f3d1ce..09364cd23 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -668,6 +668,17 @@ let {{
decoder_output += ImmOpConstructor.subst(setendIop)
exec_output += PredOpExecute.subst(setendIop)
+ clrexCode = '''
+ unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
+ fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
+ '''
+ clrexIop = InstObjParams("clrex", "Clrex","PredOp",
+ { "code": clrexCode,
+ "predicate_test": predicateTest },[])
+ header_output += BasicDeclare.subst(clrexIop)
+ decoder_output += BasicConstructor.subst(clrexIop)
+ exec_output += PredOpExecute.subst(clrexIop)
+
cpsCode = '''
uint32_t mode = bits(imm, 4, 0);
uint32_t f = bits(imm, 5);