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author | Matt Horsnell <Matt.Horsnell@ARM.com> | 2011-01-18 16:30:05 -0600 |
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committer | Matt Horsnell <Matt.Horsnell@ARM.com> | 2011-01-18 16:30:05 -0600 |
commit | adbd84ab9fffdcdce18f564acffa508c10164c9f (patch) | |
tree | aa6d90545a22e3524e33022176666569a47d83ba /src/arch/arm/isa/insts | |
parent | 11bef2ab3811e5c7a65d33ba86718d8c606be87a (diff) | |
download | gem5-adbd84ab9fffdcdce18f564acffa508c10164c9f.tar.xz |
ARM: The ARM decoder should not panic when decoding undefined holes is arch.
This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 79 |
1 files changed, 53 insertions, 26 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index a2948b90a..5aca525a4 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -871,14 +871,21 @@ let {{ if readDest: readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' - assert(imm >= 0 && imm < eCount); - for (unsigned i = 0; i < eCount; i++) { - Element srcElem1 = gtoh(srcReg1.elements[i]); - Element srcElem2 = gtoh(srcReg2.elements[imm]); - Element destElem; - %(readDest)s - %(op)s - destReg.elements[i] = htog(destElem); + if (imm < 0 && imm >= eCount) { +#if FULL_SYSTEM + fault = new UndefinedInstruction; +#else + fault = new UndefinedInstruction(false, mnemonic); +#endif + } else { + for (unsigned i = 0; i < eCount; i++) { + Element srcElem1 = gtoh(srcReg1.elements[i]); + Element srcElem2 = gtoh(srcReg2.elements[imm]); + Element destElem; + %(readDest)s + %(op)s + destReg.elements[i] = htog(destElem); + } } ''' % { "op" : op, "readDest" : readDestCode } for reg in range(rCount): @@ -919,14 +926,21 @@ let {{ if readDest: readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' - assert(imm >= 0 && imm < eCount); - for (unsigned i = 0; i < eCount; i++) { - Element srcElem1 = gtoh(srcReg1.elements[i]); - Element srcElem2 = gtoh(srcReg2.elements[imm]); - BigElement destElem; - %(readDest)s - %(op)s - destReg.elements[i] = htog(destElem); + if (imm < 0 && imm >= eCount) { +#if FULL_SYSTEM + fault = new UndefinedInstruction; +#else + fault = new UndefinedInstruction(false, mnemonic); +#endif + } else { + for (unsigned i = 0; i < eCount; i++) { + Element srcElem1 = gtoh(srcReg1.elements[i]); + Element srcElem2 = gtoh(srcReg2.elements[imm]); + BigElement destElem; + %(readDest)s + %(op)s + destReg.elements[i] = htog(destElem); + } } ''' % { "op" : op, "readDest" : readDestCode } for reg in range(2 * rCount): @@ -965,14 +979,21 @@ let {{ if readDest: readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' - assert(imm >= 0 && imm < rCount); - for (unsigned i = 0; i < rCount; i++) { - FloatReg srcReg1 = srcRegs1[i]; - FloatReg srcReg2 = srcRegs2[imm]; - FloatReg destReg; - %(readDest)s - %(op)s - destRegs[i] = destReg; + if (imm < 0 && imm >= eCount) { +#if FULL_SYSTEM + fault = new UndefinedInstruction; +#else + fault = new UndefinedInstruction(false, mnemonic); +#endif + } else { + for (unsigned i = 0; i < rCount; i++) { + FloatReg srcReg1 = srcRegs1[i]; + FloatReg srcReg2 = srcRegs2[imm]; + FloatReg destReg; + %(readDest)s + %(op)s + destRegs[i] = destReg; + } } ''' % { "op" : op, "readDest" : readDestCode } for reg in range(rCount): @@ -3277,8 +3298,14 @@ let {{ destReg.elements[i] = srcReg1.elements[index]; } else { index -= eCount; - assert(index < eCount); - destReg.elements[i] = srcReg2.elements[index]; + if (index >= eCount) +#if FULL_SYSTEM + fault = new UndefinedInstruction; +#else + fault = new UndefinedInstruction(false, mnemonic); +#endif + else + destReg.elements[i] = srcReg2.elements[index]; } } ''' |