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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2017-10-23 10:54:16 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-15 14:16:57 +0000 |
| commit | 1a551746a00501331ccde9eeb19a8fb5ca8982a2 (patch) | |
| tree | a0e43bd5bca9f2bacb6ed18652f312bc5bcddd3c /src/arch/arm/isa/insts | |
| parent | ccdbc394e2f4adcb8a3b89b8df7ce403b9fbd937 (diff) | |
| download | gem5-1a551746a00501331ccde9eeb19a8fb5ca8982a2.tar.xz | |
arch-arm: Dsb instruction shouldn't flush the pipeline
DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter
attribute will be removed for either the 32 and 64 bit version.
Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5363
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc64.isa | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index b42c9f9dd..80ad6cdf4 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1090,8 +1090,7 @@ let {{ dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", {"code": dsbCode, "predicate_test": predicateTest}, - ['IsMemBarrier', 'IsSerializeAfter', - 'IsSquashAfter']) + ['IsMemBarrier', 'IsSerializeAfter']) header_output += ImmOpDeclare.subst(dsbIop) decoder_output += ImmOpConstructor.subst(dsbIop) exec_output += PredOpExecute.subst(dsbIop) diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index ac9f0a960..58f08f51e 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -146,8 +146,7 @@ let {{ exec_output += BasicExecute.subst(isbIop) dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "", - ['IsMemBarrier', 'IsSerializeAfter', - 'IsSquashAfter']) + ['IsMemBarrier', 'IsSerializeAfter']) header_output += BasicDeclare.subst(dsbIop) decoder_output += BasicConstructor64.subst(dsbIop) exec_output += BasicExecute.subst(dsbIop) |