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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-20 12:13:08 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2018-02-07 16:14:39 +0000 |
| commit | 4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa (patch) | |
| tree | 987d4e9038f71deab52cf814fd0f303609835201 /src/arch/arm/isa/insts | |
| parent | 760e2eb6f4e40080a49e6372284c5213bf95475a (diff) | |
| download | gem5-4d9811cc5fd36a972e340ad82b14ab0ccaeb5cfa.tar.xz | |
arch-arm: Fix printing of the data cache maintenance instructions
Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7825
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 18 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 41e36d350..dd87bed62 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -417,7 +417,7 @@ let {{ ''' - msrDCZVAIop = InstObjParams("dczva", "Dczva", "SysDC64", + msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64", { "ea_code" : msrdczva_ea_code, "memacc_code" : ";", "use_uops" : 0, "op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']); diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 8745e86bc..cf3d0e00f 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2013,2017 ARM Limited +// Copyright (c) 2010-2013,2017-2018 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -1073,8 +1073,8 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDcimvacIop = InstObjParams("mcr dcimvac", "McrDcimvac", - "MiscRegRegImmMemOp", + McrDcimvacIop = InstObjParams("mcr", "McrDcimvac", + "MiscRegRegImmOp", {"memacc_code": McrDcCheckCode, "postacc_code": "", "ea_code": McrDcimvacCode, @@ -1092,8 +1092,8 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDccmvacIop = InstObjParams("mcr dccmvac", "McrDccmvac", - "MiscRegRegImmMemOp", + McrDccmvacIop = InstObjParams("mcr", "McrDccmvac", + "MiscRegRegImmOp", {"memacc_code": McrDcCheckCode, "postacc_code": "", "ea_code": McrDccmvacCode, @@ -1111,8 +1111,8 @@ let {{ Request::DST_POU); EA = Op1; ''' - McrDccmvauIop = InstObjParams("mcr dccmvau", "McrDccmvau", - "MiscRegRegImmMemOp", + McrDccmvauIop = InstObjParams("mcr", "McrDccmvau", + "MiscRegRegImmOp", {"memacc_code": McrDcCheckCode, "postacc_code": "", "ea_code": McrDccmvauCode, @@ -1131,8 +1131,8 @@ let {{ Request::DST_POC); EA = Op1; ''' - McrDccimvacIop = InstObjParams("mcr dccimvac", "McrDccimvac", - "MiscRegRegImmMemOp", + McrDccimvacIop = InstObjParams("mcr", "McrDccimvac", + "MiscRegRegImmOp", {"memacc_code": McrDcCheckCode, "postacc_code": "", "ea_code": McrDccimvacCode, |