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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:04 -0500 |
| commit | 05d880f7a1326f83076614442bc38c5332624dd4 (patch) | |
| tree | ef800538a7919f9d57c300b1d0b4bf80d7619b76 /src/arch/arm/isa/insts | |
| parent | d8294575e15a71354a9967afba9c9365908c100e (diff) | |
| download | gem5-05d880f7a1326f83076614442bc38c5332624dd4.tar.xz | |
ARM: Restrict the shift amount from a register to 8 bits.
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
Diffstat (limited to 'src/arch/arm/isa/insts')
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index f96416168..daac4ed3c 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -96,7 +96,7 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" def buildDataInst(mnem, code, flagType = "logic"): global header_output, decoder_output, exec_output |