ARM: Take advantage of new PCState syntax.

5 files changed, 35 insertions, 71 deletions

diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 3ff9042e6..d8ea2118e 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -46,17 +46,14 @@ let {{
     # B, BL
     for (mnem, link) in (("b", False), ("bl", True)):
         bCode = '''
-        ArmISA::PCState pc = PCS;
-        Addr curPc = pc.instPC();
-        pc.instNPC((uint32_t)(curPc + imm));
-        PCS = pc;
+        NPC = (uint32_t)(PC + imm);
         '''
         if (link):
             bCode += '''
-                if (pc.thumb())
-                    LR = curPc | 1;
+                if (Thumb)
+                    LR = PC | 1;
                 else
-                    LR = curPc - 4;
+                    LR = PC - 4;
             '''
 
         bIop = InstObjParams(mnem, mnem.capitalize(), "BranchImmCond",
@@ -68,12 +65,9 @@ let {{
 
     # BX, BLX
     blxCode = '''
-    ArmISA::PCState pc = PCS;
-    Addr curPc M5_VAR_USED = pc.instPC();
     %(link)s
     // Switch modes
     %(branch)s
-    PCS = pc;
     '''
 
     blxList = (("blx", True, True),
@@ -85,8 +79,8 @@ let {{
         if imm:
             Name += "Imm"
             # Since we're switching ISAs, the target ISA will be the opposite
-            # of the current ISA. pc.thumb() is whether the target is ARM.
-            newPC = '(pc.thumb() ? (roundDown(curPc, 4) + imm) : (curPc + imm))'
+            # of the current ISA. Thumb is whether the target is ARM.
+            newPC = '(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
             base = "BranchImmCond"
             declare = BranchImmCondDeclare
             constructor = BranchImmCondConstructor
@@ -101,28 +95,28 @@ let {{
                 // The immediate version of the blx thumb instruction
                 // is 32 bits wide, but "next pc" doesn't reflect that
                 // so we don't want to substract 2 from it at this point
-                if (pc.thumb())
-                    LR = curPc  | 1;
+                if (Thumb)
+                    LR = PC  | 1;
                 else
-                    LR = curPc - 4;
+                    LR = PC - 4;
             '''
         elif link:
             linkStr = '''
-                if (pc.thumb())
-                    LR = (curPc - 2) | 1;
+                if (Thumb)
+                    LR = (PC - 2) | 1;
                 else
-                    LR = curPc - 4;
+                    LR = PC - 4;
             '''
         else:
             linkStr = ""
 
         if imm and link: #blx with imm
             branchStr = '''
-                pc.nextThumb(!pc.thumb());
-                pc.instNPC(%(newPC)s);
+                NextThumb = !Thumb;
+                NPC = %(newPC)s;
             '''
         else:
-            branchStr = "pc.instIWNPC(%(newPC)s);"
+            branchStr = "IWNPC = %(newPC)s;"
         branchStr = branchStr % { "newPC" : newPC }
 
         code = blxCode % {"link": linkStr,
@@ -139,12 +133,7 @@ let {{
 
     #CBNZ, CBZ. These are always unconditional as far as predicates
     for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
-        code = '''
-        ArmISA::PCState pc = PCS;
-        Addr curPc = pc.instPC();
-        pc.instNPC((uint32_t)(curPc + imm));
-        PCS = pc;
-        '''
+        code = 'NPC = (uint32_t)(PC + imm);\n'
         predTest = "Op1 %(test)s 0" % {"test": test}
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
                             {"code": code, "predicate_test": predTest})
@@ -161,11 +150,7 @@ let {{
                                       ArmISA::TLB::MustBeOne;
             EA = Op1 + Op2 * 2
             '''
-            accCode = '''
-            ArmISA::PCState pc = PCS;
-            pc.instNPC(pc.instPC() + 2 * (Mem.uh));
-            PCS = pc;
-            '''
+            accCode = 'NPC = PC + 2 * (Mem.uh);\n'
             mnem = "tbh"
         else:
             eaCode = '''
@@ -174,11 +159,7 @@ let {{
                                       ArmISA::TLB::MustBeOne;
             EA = Op1 + Op2
             '''
-            accCode = '''
-            ArmISA::PCState pc = PCS;
-            pc.instNPC(pc.instPC() + 2 * (Mem.ub));
-            PCS = pc;
-            '''
+            accCode = 'NPC = PC + 2 * (Mem.ub)'
             mnem = "tbb"
         iop = InstObjParams(mnem, mnem.capitalize(), "BranchRegReg",
                             {'ea_code': eaCode,
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 4d368e181..26b6bfc92 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -239,10 +239,8 @@ let {{
                 cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
             Cpsr = ~CondCodesMask & newCpsr;
             CondCodes = CondCodesMask & newCpsr;
-            ArmISA::PCState pc = PCS;
-            pc.nextThumb(((CPSR)newCpsr).t);
-            pc.nextJazelle(((CPSR)newCpsr).j);
-            PCS = pc;
+            NextThumb = ((CPSR)newCpsr).t;
+            NextJazelle = ((CPSR)newCpsr).j;
             '''
             buildImmDataInst(mnem + 's', code, flagType,
                              suffix = "ImmPclr", buildCc = False,
@@ -257,8 +255,7 @@ let {{
     buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
     buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
     buildImmDataInst("adr", '''
-                               ArmISA::PCState pc = PCS;
-                               Dest = resTemp = (pc.instPC() & ~0x3) +
+                               Dest = resTemp = (PC & ~0x3) +
                                (op1 ? secondOp : -secondOp);
                             ''')
     buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index b091da856..21601f7d3 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -105,16 +105,15 @@ let {{
             accCode = '''
             CPSR cpsr = Cpsr;
             SCTLR sctlr = Sctlr;
-            ArmISA::PCState pc = PCS;
-            pc.instNPC(cSwap<uint32_t>(Mem.ud, cpsr.e));
+            // Use the version of NPC that gets set before NextThumb
+            pNPC = cSwap<uint32_t>(Mem.ud, cpsr.e);
             uint32_t newCpsr =
                 cpsrWriteByInstr(cpsr | CondCodes,
                                  cSwap<uint32_t>(Mem.ud >> 32, cpsr.e),
                                  0xF, true, sctlr.nmfi);
             Cpsr = ~CondCodesMask & newCpsr;
-            pc.nextThumb(((CPSR)newCpsr).t);
-            pc.nextJazelle(((CPSR)newCpsr).j);
-            PCS = pc;
+            NextThumb = ((CPSR)newCpsr).t;
+            NextJazelle = ((CPSR)newCpsr).j;
             CondCodes = CondCodesMask & newCpsr;
             '''
             self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index a81050b1e..6bf789efd 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -93,9 +93,7 @@ let {{
             cpsrWriteByInstr(cpsr | CondCodes, Spsr, 0xF, true, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
         CondCodes = CondCodesMask & newCpsr;
-        ArmISA::PCState pc = PCS;
-        pc.instIWNPC(cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0));
-        PCS = pc;
+        IWNPC = cSwap(Mem.uw, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
     '''
     microLdrRetUopIop = InstObjParams('ldr_ret_uop', 'MicroLdrRetUop',
                                       'MicroMemOp',
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 6e6d2594c..a1cf895f8 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -83,10 +83,8 @@ let {{
         uint32_t newCpsr =
             cpsrWriteByInstr(Cpsr | CondCodes, Op1, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
-        ArmISA::PCState pc = PCS;
-        pc.nextThumb(((CPSR)newCpsr).t);
-        pc.nextJazelle(((CPSR)newCpsr).j);
-        PCS = pc;
+        NextThumb = ((CPSR)newCpsr).t;
+        NextJazelle = ((CPSR)newCpsr).j;
         CondCodes = CondCodesMask & newCpsr;
     '''
     msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
@@ -111,10 +109,8 @@ let {{
         uint32_t newCpsr =
             cpsrWriteByInstr(Cpsr | CondCodes, imm, byteMask, false, sctlr.nmfi);
         Cpsr = ~CondCodesMask & newCpsr;
-        ArmISA::PCState pc = PCS;
-        pc.nextThumb(((CPSR)newCpsr).t);
-        pc.nextJazelle(((CPSR)newCpsr).j);
-        PCS = pc;
+        NextThumb = ((CPSR)newCpsr).t;
+        NextJazelle = ((CPSR)newCpsr).j;
         CondCodes = CondCodesMask & newCpsr;
     '''
     msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
@@ -470,10 +466,7 @@ let {{
     decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop)
     exec_output += PredOpExecute.subst(usada8Iop)
 
-    bkptCode = '''
-    ArmISA::PCState pc = PCS;
-    return new PrefetchAbort(pc.pc(), ArmFault::DebugEvent);
-    '''
+    bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n'
     bkptIop = InstObjParams("bkpt", "BkptInst", "ArmStaticInst",
             bkptCode)
     header_output += BasicDeclare.subst(bkptIop)
@@ -650,10 +643,8 @@ let {{
     exec_output += PredOpExecute.subst(mcr15UserIop)
 
     enterxCode = '''
-        ArmISA::PCState pc = PCS;
-        pc.nextThumb(true);
-        pc.nextJazelle(true);
-        PCS = pc;
+        NextThumb = true;
+        NextJazelle = true;
     '''
     enterxIop = InstObjParams("enterx", "Enterx", "PredOp",
                               { "code": enterxCode,
@@ -663,10 +654,8 @@ let {{
     exec_output += PredOpExecute.subst(enterxIop)
 
     leavexCode = '''
-        ArmISA::PCState pc = PCS;
-        pc.nextThumb(true);
-        pc.nextJazelle(false);
-        PCS = pc;
+        NextThumb = true;
+        NextJazelle = false;
     '''
     leavexIop = InstObjParams("leavex", "Leavex", "PredOp",
                               { "code": leavexCode,