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authorMitch Hayenga <mitch.hayenga@arm.com>2016-10-13 19:22:10 +0100
committerMitch Hayenga <mitch.hayenga@arm.com>2016-10-13 19:22:10 +0100
commitbd0c2d5b0bf512aa5c172fe5676e151913e5e97d (patch)
tree3aa61e0e7070664b605c216dff51f8d4d6847d8f /src/arch/arm/isa/insts
parent68fdccb30bd85cd99823fb411ec7ae67112062d7 (diff)
downloadgem5-bd0c2d5b0bf512aa5c172fe5676e151913e5e97d.tar.xz
isa,arm: Add missing AArch32 FP instructions
This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Diffstat (limited to 'src/arch/arm/isa/insts')
-rw-r--r--src/arch/arm/isa/insts/fp.isa62
1 files changed, 61 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 34dff5139..0f10a05af 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013 ARM Limited
+// Copyright (c) 2010-2013,2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -642,6 +642,26 @@ let {{
"-FpOp1", "-dbl(FpOp1P0_uw, FpOp1P1_uw)")
buildSimpleUnaryFpOp("vabs", "Vabs", "FpRegRegOp", "SimdFloatMiscOp",
"fabsf(FpOp1)", "fabs(dbl(FpOp1P0_uw, FpOp1P1_uw))")
+ buildSimpleUnaryFpOp("vrintp", "VRIntP", "FpRegRegOp", "SimdFloatMiscOp",
+ "fplibRoundInt<uint32_t>(FpOp1, FPRounding_POSINF, false, fpscr)",
+ "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
+ "FPRounding_POSINF, false, fpscr)"
+ )
+ buildSimpleUnaryFpOp("vrintm", "VRIntM", "FpRegRegOp", "SimdFloatMiscOp",
+ "fplibRoundInt<uint32_t>(FpOp1, FPRounding_NEGINF, false, fpscr)",
+ "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
+ "FPRounding_NEGINF, false, fpscr)"
+ )
+ buildSimpleUnaryFpOp("vrinta", "VRIntA", "FpRegRegOp", "SimdFloatMiscOp",
+ "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEAWAY, false, fpscr)",
+ "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
+ "FPRounding_TIEAWAY, false, fpscr)"
+ )
+ buildSimpleUnaryFpOp("vrintn", "VRIntN", "FpRegRegOp", "SimdFloatMiscOp",
+ "fplibRoundInt<uint32_t>(FpOp1, FPRounding_TIEEVEN, false, fpscr)",
+ "fplibRoundInt<uint64_t>(dbl(FpOp1P0_uw, FpOp1P1_uw), " \
+ "FPRounding_TIEEVEN, false, fpscr)"
+ )
}};
let {{
@@ -1408,6 +1428,46 @@ let {{
decoder_output = ""
exec_output = ""
+ vselSCode = vfpEnabledCheckCode + '''
+ if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) {
+ FpDest = FpOp1;
+ } else {
+ FpDest = FpOp2;
+ } '''
+
+ vselSIop = InstObjParams("vsels", "VselS", "FpRegRegRegCondOp",
+ { "code" : vselSCode,
+ "predicate_test" : predicateTest,
+ "op_class" : "SimdFloatCmpOp" }, [] )
+ header_output += FpRegRegRegCondOpDeclare.subst(vselSIop);
+ decoder_output += FpRegRegRegCondOpConstructor.subst(vselSIop);
+ exec_output += PredOpExecute.subst(vselSIop);
+
+ vselDCode = vfpEnabledCheckCode + '''
+ if (testPredicate(CondCodesNZ, CondCodesC, CondCodesV, cond)) {
+ FpDestP0_uw = FpOp1P0_uw;
+ FpDestP1_uw = FpOp1P1_uw;
+ } else {
+ FpDestP0_uw = FpOp2P0_uw;
+ FpDestP1_uw = FpOp2P1_uw;
+ } '''
+
+ vselDIop = InstObjParams("vseld", "VselD", "FpRegRegRegCondOp",
+ { "code" : vselDCode,
+ "predicate_test" : predicateTest,
+ "op_class" : "SimdFloatCmpOp" }, [] )
+ header_output += FpRegRegRegCondOpDeclare.subst(vselDIop);
+ decoder_output += FpRegRegRegCondOpConstructor.subst(vselDIop);
+ exec_output += PredOpExecute.subst(vselDIop);
+}};
+
+
+let {{
+
+ header_output = ""
+ decoder_output = ""
+ exec_output = ""
+
vcvtFpSFixedSCode = vfpEnabledCheckCode + '''
FPSCR fpscr = (FPSCR) FpscrExc;
vfpFlushToZero(fpscr, FpOp1);